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Lecture 3.2 - Counters
Asynchronous ripple counter
This one is easy to implement and understand, but the outputs do not all change simultaneously. It takes some finite time for transistors to change state, and thus for each flip-flop to alter its output, which is the clock input for the next flip-flop.
Each T flip-flop divides its clock input frequency by two. Cascading them produces slower and slower frequency outputs. Note that here we clock each flip-flop directly off the output of the preceding flip-flop, whereas in the lecture notes there is a NOT gate on the output. This is because the flip-flops used here are trailing edge triggered, meaning that they change when the clock drops low. Most flip-flops are leading edge triggered, meaning that they change when the clock goes high.
This counter has the advantage that all the outputs change at the same time because all the flip-flops are clocked from the same signal. Each T flip-flop is toggled only when all the lower bit flip-flops are high.