Lecture 3.1 - Flip-Flops and Latches

SR latch

When Set goes high the output Q goes high. When Reset goes high Q goes low. When Set and Reset are both low Q stays at its previous value.

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~S~R latch

The ~S~R latch operates like the SR latch, except the Set and Reset inputs are inverted.

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D latch

The D latch copies the input on the D line whenever the enable line is high.

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D-type master-slave flip-flop

This is the opaque version of the D-type latch. The input is copied to the output just as the enable (clock) line goes high. It is composed of two D-type latches which are enabled at opposite times during the clock cycle. This prevents inputs from being transparently copied to the output, except when the clock transitions to high.

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Sandbox

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The digital logic simulator used above is SimcirJS, which is licenced under the MIT Licence.